The present invention disclosed herein relates to a nonvolatile semiconductor memory device, and more particularly, to a flash memory device including a voltage regulator supplying a reference voltage.
Semiconductor memory devices are storage devices that store data and read the stored data when necessary. Semiconductor memory devices are categorized into random access memory (RAM) as a volatile memory device and read only memory (ROM) as a nonvolatile memory device. Examples of RAM include a dynamic RAM (DRAM) and a static RAM (SRAM), and examples of ROM include a flash memory device, a programmable ROM (PROM), an erasable PROM (EPROM), and an electrically EPROM (EEPROM).
Flash memory devices are a type of ROM. Since the flash memory devices have low power consumption and can read and write data freely, they are suitable for digital cameras, mobile phones, personal digital assistants (PDAs), and so on. In addition, flash memory devices are categorized into NAND flash memory devices and NOR flash memory devices according to the structure of a memory cell array. The NAND flash memory devices are memory devices for data storage and are mainly used in USB storage devices or MP3 players. Meanwhile, the NOR flash memory devices are memory devices for code storage and are used in mobile phone terminals requiring high-speed data processing because of their fast processing speed.
Recent NOR flash memory devices can store multi-bit data in one memory cell. Such NOR flash memory devices execute a program operation based on an incremental step pulse program (ISPP), and use a bit scan method for increasing a program speed.
The bit scan method is a method which searches data “0” in input data and simultaneously programs the searched data “0” on the basis of predetermined bit number. The bit scan method can increase the program speed and reduce the program time.
As one of known technical documents, there is Japanese Patent Publication No. 2006-294217.
FIG. 6 illustrates a NOR flash memory device disclosed in Japanese Patent Publication No. 2006-294217. Referring to FIG. 6, the NOR flash memory device 100 includes a plurality of memory cells 110, a word line voltage generation circuit 105, a data input buffer 150, a scan controller 140, a scanning data latch circuit 130, and a write driver circuit 120. Upon program operation, the word line voltage generation circuit 105 generates a step voltage to a word line WL commonly connected to the plurality of memory cells 110. The step voltage refers to a stepwise increasing voltage. Data to be written to the plurality of memory cells 110 are input to the data input buffer 150. The scan controller 140 searches data input to the data input buffer 150 and determines bit number of data to be simultaneously programmed to the plurality of memory cells. The scanning data latch circuit 130 latches the data searched by the scan controller 140. The write driver circuit 120 provides a write voltage to bit lines BL of the memory cells 110 according to the data latched in the scanning data latch circuit 130. Whenever the step voltage is supplied to the word line WL, the scan controller 140 can vary the bit number of the data to be simultaneously programmed, and can constantly control the number of memory cells to which a write operation is performed.
FIGS. 3 through 5 illustrate a typical NOR flash memory device. Specifically, FIG. 3 is a schematic block diagram of a typical NOR flash memory device 80 including a drain voltage regulator 8, and FIG. 4 is a circuit diagram of the drain voltage regulator 83. FIG. 5 is a graph illustrating the relation between “a current (Ipb) supplied by a voltage (Vpb)” and “number of cells to be written (WDCOUNT: an output signal of a counter circuit)”.
The memory device 80 of FIG. 3 includes a memory cell array 81 in which rows (word lines WL0 to WLi) and columns (bit lines BL0 to BLj) are arranged in a matrix form. A write circuit 84, a count circuit 85, and a write buffer 86 are serially connected to the memory cell array 81.
In addition, a booster circuit 82 and a drain voltage regulator 83 are serially connected to the write circuit 84. The drain voltage regulator 83 regulates a high voltage Vpp generated by the booster circuit 82 to a required voltage Vpb and supplies the regulated voltage to the write circuit 84.
FIG. 4 is a circuit diagram of the drain voltage generator 83. The drain voltage regulator 83 includes a comparator COMP, a PMOS transistor PM-1 resistors R1 and R0 used as a divider, a PMOS transistor PM-2 receiving a write enable signal WEN, and NMOS transistors NM-1 and NM-2.
The comparator COMP determines whether an output voltage VDIV of the divider is higher or lower than the reference voltage VREF. The PMOS transistor PM-1 operates according to the determination result of the comparator COMP.
In the drain voltage regulator 83 of FIG. 4, the PMOS transistor PM-1 has a gate connected to the comparator COMP, a drain connected to the high voltage Vpp through the PMOS transistor PM-2, and a source grounded through the NMOS transistor NM-1 and the resistors R1 and R0.
The NMOS transistor NM-2 has a gate connected to the source of the PMOS transistor PM-1, a drain connected to the high voltage Vpp through the PMOS transistor PM-2, and a source connected to an output terminal of the voltage Vpb.
Also, the PMOS transistor PM-2 has a gate receiving the write enable signal EN, and a drain connected to the high voltage Vpp.
Also, the NMOS transistor NM-1 has a drain and a gate commonly connected to the source of the PMOS transistor PM-1, and a source grounded through the resistors R1 and R0.
As illustrated in FIG. 4. the typical NOR flash memory device always performs the same operation, regardless of the write bit number.
FIG. 5 is a graph illustrating the relation between “a current (Ipb) supplied by a voltage (Vpb)” and “number of cells to be written (WDCOUNT: an output signal of a counter circuit)” in the typical NOR flash memory device. The bit number is proportional to the current.
In practice, however, the voltage level of the voltage Vpb varies because an amount of current supplied from the voltage Vpb is different according to the write bit number.
For example, if the write bit number is 1 bit and the number of cells to be written simultaneously is 1, Ipb=Icell, where Ipb is a current supplied from the voltage Vpb and Icell is a current flowing through the drain-source path of the memory cell in the write operation.
If the write bit number is 16 bits and the number of cells to be written simultaneously is 16, Ipb=16×Icell, where Ipb is a current supplied from the voltage Vpb and Icell is a current flowing through the drain-source path of the memory cell in the write operation.
In this case, the NMOS transistor controlling the voltage Vpb operates as a resistive element, so that a current supply amount when the write bit number is 1 is larger than that when the write bit number is 16. Thus, the output voltage Vpb is also lowered.